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single - supply, low power, precision fet input quad buffer data sheet AD8244 features low p ower 250 a maximum supply current per amplifier fet i nput 2 pa maximum input bias current at 25 c extremely high input impedance low n oise 13 nv/hz voltage noise at 1 khz 0.4 v p - p voltage noise (0.1 hz to 10 hz) 0.8 fa/hz current noise at 1 khz high dc precision 3 v/c maximum offset drift (b grade) 3 mhz bandwidth unique pinout no leakage from inputs to supply pins provides guarding capa bility rail - to - rail output single - supply operation input range extends to ground wide supply range single - supply: 3 v to 36 v dual - supply: 1.5 v to 1 8 v available in a compact 10 - lead msop applications biopotential e lectrodes medical i nstrumentation high impedance sensor conditioning f ilters photodiode a mplifiers p in configuration in a 1 out a 2 +v s 3 out b 4 in b 5 in d 10 out d 9 ?v s 8 out c 7 in c 6 AD8244 1 1689-001 figure 1. 0.001 0.01 0.1 1 10 10 100 1k 10k 100k gain m a tching (%) frequenc y (hz) 1 1689-002 1/2 AD8244 in-am p typica l mism a tch between an y two channels figure 2. gain matching vs . frequency general description the AD8244 is a p recision, low power , fet input , quad unity - gain buffer that is designed to isolate very large sour ce impedances from the rest of the signal chain. the 2 p a maximum bias current, near zero current noise, and 1 0 t? input impedance introduce almost no e rror , even with source impedance well into the megaohms. many t raditional op erational amp lifier pin outs have a supply pin that is next to the noninverting input. a guard trace must be routed between these pins to avoid leakage currents much larger than the bias current of a fet input op amp. guard t races can be routed between pins for large packages , such as dip or even soic ; however, the board area consumed by these packages is prohibitive for many modern applications. the AD8244 solves this problem with a unique pinout that physically separates the high impedance inputs from the low impedance supplies a nd outputs of the other buffers. this configuration simplifies guarding while reducing board space , allowing high performance and high density in the same design . the AD8244 design is focused on solving problems specific to buffers . this includes close channel - to - channel matching w hich allows channels of the AD8244 to be used in differential signal chains with minimal error . with its low voltage noise, wide supply range, and high precision, the AD8244 is also flexible enough to provide high perf ormance anywhere a unity - gain buffer is needed, even with low source resistance. the AD8244 is specified over the industrial temperature range of ?40c to +85c. it is available in a 10- lead msop package . rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by imp lication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com
AD8244 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 pin configuratio n ............................................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maxim um ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 1 4 overview ...................................................................................... 14 guarding ...................................................................................... 14 input protection ......................................................................... 15 layout considerations ............................................................... 15 differ ential signal chains ......................................................... 15 low output impedance vs. frequency .................................... 15 applications information .............................................................. 16 electrocardiogram (ecg) ......................................................... 16 filtering ........................................................................................ 16 photodiode amplifier ................................................................ 17 low noise, jfet input buffer .................................................. 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 10 /13 revision 0: initial version rev. 0 | page 2 of 20
data sheet AD8244 specifications + v s = 5 v , C v s = 0 v , t a = 25c, v in = 0 .2 v, r l = 10 k? to g round , unless otherwise noted. table 1 . parameter test conditions/comments AD8244 a AD8244 b unit min typ max min typ max dc performance offset voltage 100 600 100 350 v over temperature t a = ?40c to +85c 1 .25 0. 675 mv average t emperature coefficient t a = ?40c to +85c 1 0 5 v/c offset voltage matching channel to channel 8 00 5 0 0 v input bias current 0.5 10 0.5 2 pa over temperature t a = 85c 150 50 p a input bias current matching channel to channel 0. 05 0.05 0. 2 pa over temperature t a = 85c 2 2 p a system performance nominal gain 1 1 v/v system error 1 v out = 0.2 v to 3 v 0.08 0.05 % average temperature coefficient t a = ?40c to +85c 2 1 ppm/c gain matching channel to channel 0.10 0.08 % noise performance voltage noise spectral density f = 1 khz 1 3 1 3 nv/hz peak -to - peak f = 0.1 hz to 10 hz 0.4 0.4 2 v p -p current noise spectral density f = 1 khz 0.8 0.8 fa/hz peak -to - peak f = 0.1 hz to 10 hz 8 8 fa p -p dynamic performance small signal bandwidth ?3 db 3 3 mhz slew rate 0.8 0.8 v/s settling time to 0.01% v out = 0.2 v to 3 v 8 8 s input characteristics input voltage range 2 0 4 0 4 v over temperature t a = ?40c to +85c 0 3.5 0 3.5 v input impedance 3 10||4 10||4 t||pf output characteristics output swing r l = 10 k to ground 0.025 4.9 0.025 4.9 v over temperature t a = ?40c to +85c 0.03 4.88 0.03 4.88 v output swing r l = no load 0.025 4.97 0.025 4.97 v over temperature t a = ?40c to +85c 0.03 4.95 0.03 4.95 v short - circuit current 8 8 ma capacitive load drive 200 200 pf power supply operating range single supply 3 36 3 36 v dual supply 1.5 18 1.5 18 v power supply rejection v in = 2.5 v, +v s = 4.5 v to 5.5 v 80 80 db supply current per amplifier i out = 0 ma 180 2 5 0 180 250 a over temperature t a = ?40c to +85c 300 300 a temperature range specified performance ?40 +85 ?40 +85 c 1 error as a percentage of the measurement. this includes the effects of open - loop gain and common - mode rejection ratio . 2 the inputs of the AD8244 can go up to the positive supply; however, the input range is derated because error increases near the positive supply as the input transis tors start to saturate. the inputs also maintain high impedance when driven slightly below ground. 3 for more information on the input impedance, see figure 24 and figure 37. rev. 0 | page 3 of 20
AD8244 data sheet v s = 5 v, t a = 25c, v in = 0 v, r l = 10 k?, unless otherwise noted. table 2 . parameter test conditions/comments AD8244 a AD8244 b unit min typ max min typ max dc performance offset voltage 100 600 100 350 v over temperature t a = ?40c to +85c 1 .25 0. 675 mv average temperature coefficient t a = ?40c to +85c 1 0 5 v/c offset voltage matching channel to channel 8 00 5 0 0 v input bias current 0.5 10 0.5 2 pa over temperature t a = 85c 150 50 pa input bias current matching channel to channel 0.05 0.05 0.2 pa over temperature t a = 85c 2 2 pa system performance nominal gain 1 1 v/v system error 1 v out = ?3 v to +3 v 0.05 0.03 % average temperature coefficient t a = ?40c to +85c 2 1 ppm/c gain matching channel to channel 0.08 0.05 % nonlinearity v out = ?3 v to +3 v 20 20 ppm noise performance voltage noise spectral density f = 1 khz 13 13 nv/hz peak -to - peak f = 0.1 hz to 10 hz 0.4 0. 4 2 v p -p current noise spectral density f = 1 khz 0.8 0.8 fa/hz peak -to - peak f = 0.1 hz to 10 hz 8 8 fa p -p dynamic performance small signal bandwidth ?3 db 3.3 3.3 mhz slew rate 0.8 0.8 v/s settling time to 0.01% v out = ?3 v to +3 v 14 14 s input characteristics input voltage range 2 ?5 +4 ?5 +4 v over temperature t a = ?40c to +85c C 5 +3.5 C 5 +3.5 v input impedance 3 10||4 10||4 t||pf output characteristics output swing r l = 10 k ?4.9 +4.9 ?4.9 +4.9 v over temperature t a = ?40c to +85c C 4.88 +4.88 C 4.88 +4.88 v output swing r l = no load ?4.975 +4.97 ?4.975 +4.97 v over temperature t a = ?40c to +85c C 4.95 +4.95 C 4.95 +4.95 v short - circuit current 10 10 ma capacitive load drive 200 200 pf power supply operating range single supply 3 36 3 36 v dual supply 1.5 18 1.5 18 v power supply rejection v s = 3 v to 18 v 90 80 90 db supply current per amplifier i out = 0 ma 180 2 5 0 180 250 a over temperature t a = ?40c to +85c 30 0 30 0 a temperature range specified performance t a ?40 +85 ?40 +85 c 1 error as a percentage of the measurement. this includes the effects of open - loop gain and common - mode rejection ratio . 2 the inputs of the AD8244 can go up to the positive supply; however, the input range is derated because error increases near the positive supply as the input transistors start to saturate. 3 for more information on the input impedan ce, see figure 24 and figure 37. rev. 0 | page 4 of 20
data sheet AD8244 v s = 15 v, t a = 25c, v in = 0 v, r l = 10 k?, unless otherwise noted. table 3 . parameter test conditions/comments AD8244 a AD8244 b unit min typ max min typ max dc performance offset voltage 100 600 100 350 v over temperature t a = ?40c to +85c 1 .25 0.5 45 mv average temperature coefficient t a = ?40c to +85c 1 0 3 v/c offset voltage matching channel to channel 8 00 500 v input bias current 0. 9 10 0. 9 3 pa over temperature t a = 85c 150 100 pa input bias current matching channel to channel 0.05 0. 05 0.2 pa over temperature t a = 85c 2 2 pa system performance nominal gain 1 1 v/v system error 1 v out = ?10 v to +10 v 0.03 0.0 08 % average temperature coefficient t a = ?40c to +85c 2 1 ppm/c gain matching channel to channel 0.05 0.0 1 % nonlinearity v out = ?10 v to +10 v 5 5 ppm noise performance voltage noise spectral density f = 1 khz 1 3 13 nv/hz peak -to - peak f = 0.1 hz to 10 hz 0.4 0.4 v p -p current noise spectral density f = 1 khz 0.8 0.8 fa/hz peak -to - peak f = 0.1 hz to 10 hz 8 8 fa p -p dynamic performance small signal bandwidth ?3 db 3.6 3.6 mhz slew rate 0.8 0.8 v/s settling time to 0.01% v out = ?10 v to +10 v 18 18 s input characteristics input voltage range 2 ?15 +14 ?15 +14 v over temperature t a = ?40c to +85c C 15 +13.5 C 15 +13.5 v input impedance 3 10||4 10||4 t||pf output characteristics output swing r l = 10 k ?14.87 +14.87 ?14.87 +14.87 v over temperature t a = ?40c to +85c C 14.84 +14.84 C 14.84 +14.84 v output swing r l = no load ?14.95 +14.95 ?14.95 +14.95 v over temperature t a = ?40c to +85c C 14.93 +14.93 C 14.93 +14.93 v short - circuit current 20 20 ma capacitive load drive 200 200 pf power supply operating range single supply 3 36 3 36 v dual supply 1.5 18 1.5 18 v power supply rejection v s = 3 v to 18 v 90 80 90 db supply current per amplifier i out = 0 ma 180 250 180 250 a over temperature t a = ?40c to +85c 30 0 30 0 a temperature range specified performance t a ?40 +85 ?40 +85 c 1 error as a percentage of the measurement. this includes the effects of open - loop gain and common - mode rejection ratio . 2 the inputs of the AD8244 can go up to the positive supply; however, the input range is derated because error increases near the positive supply as the input transistors start to saturate. 3 for more information on the input impedance, see fi gure 24 and figure 37. rev. 0 | page 5 of 20
AD8244 data sheet absolute maximum rat ings table 4 . parameter rating supply voltage 18 v output short - circuit current duration indefinite maximum voltage at in x or out x 1 + v s + 0.3 v min imum voltage at in x or out x 1 ?v s ? 0.3 v storage temperature range ?65c to +150c operating temperature range ?40c to + 85c maximum junction temperature 150c esd human body model (hbm) 3 kv charged device model (cdm) 1.25 kv machine model (mm) 100 v 1 for voltages beyond these limits, use input protection resistors. see the input protection section for more information. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is spec ified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 5 . thermal resistance package type ja unit 10- lead msop 1 52 c/w esd caution rev. 0 | page 6 of 20
data sheet AD8244 pin configuration an d function descripti ons in a 1 out a 2 +v s 3 out b 4 in b 5 in d 10 out d 9 ?v s 8 out c 7 in c 6 1 1689-003 AD8244 t o p view (not to scale) figure 3 . pin configuration table 6 . pin function description pin umber nemonic description 1 in a channel a input 2 out a channel a output 3 +v s positive supply voltage 4 out b channel b output 5 in b channel b input 6 in c channel c input 7 out c channel c output 8 ?v s negative supply voltage 9 out d channel d output 10 in d channel d input rev. 0 | page 7 of 20
AD8244 data sheet typical performance characteristics v s = 5 v, t a = 25c, v in = 0 v, r l = 10 k?, unless otherwise noted . ?400 ?200 0 200 400 600 0 10 20 30 40 offset vo lt age (v) hits 1 1689-004 figure 4 . typical distribution of offset voltage 1 1689-005 0 2 4 6 8 10 12 hits offset vo lt age drift (v/c) v s = 15 v t a = ? 4 0 c t o +8 5c ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 9 10 figure 5 . typical distribution of offset voltage drift 0 5 10 15 20 25 ?0.60 ?0.55 ?0.50 ?0.45 ?0.40 ?0.35 hits input bias current (pa) 1 1689-006 figure 6 . typical distribution of input bias current ?800 ?600 ?400 ?200 0 200 400 600 800 0 10 20 30 40 50 offset vo lt age m a tching (v) hits 1 1689-007 figure 7 . typical distribution of offset voltage matching ?200 ?300 ?100 0 100 200 300 0 5 10 15 20 25 30 35 40 system error (v/v) hits v in = 3v 1 1689-008 figure 8. typical distribution of system error ?20 ?40 0 20 40 60 80 0 10 20 30 40 50 psrr (v/v) hits v s = 3v t o 18v 1 1689-009 figure 9 . typical distribution of power supply rejection ratio ( psrr ) rev. 0 | page 8 of 20
data sheet AD8244 ?20 ?15 ?10 ?5 0 5 10 1k 10k 100k 1m gain (db) frequenc y (hz) v s = +3v v s = +5v v s = 5v v s = 15v 1 1689-010 figure 10 . gain vs. frequency ?20 ?15 ?10 ?5 0 5 10 1k 10k 100k 1m gain (db) frequenc y (hz) 1 1689-0 1 1 c l = 10 0p f v s = +3v v s = +5v v s = 5v v s = 15v figure 11 . gain vs . frequenc y, c l = 100 pf 0.1 1 10 100 1k 10 100 1k 10k 100k 1m output impedance (?) frequenc y (hz) 1 1689-012 figure 12 . output impedance vs . frequency 20 30 40 50 60 70 80 90 100 1 10 120 0.1 1 10 100 1k 10k psrr (db) frequenc y (hz) r e p r e s e n t a t i v e s a m p l e ? p s rr v s = 5 v v in = 0 v + p s rr v s = 5 v v in = 0 v + p s rr, s i ng l e s upp l y + v s = + 5 v , ?v s = g n d v in = + 2 . 5 v 1 1689-013 figure 13 . psrr vs. frequency 0.001 0.01 0.1 1 10 10 100 1k 10k 100k gain m a tching (%) frequenc y (hz) 1 1689-014 1/2 AD8244 in-am p typica l mism a tch between an y two channels figure 14 . gain matching vs. frequency 0.001 0.01 0.1 1 10 10 100 1k 10k 100k gain m a tching (%) frequenc y (hz) 1 1689-015 1/2 AD8244 in-am p typica l mism a tch between an y two channels figure 15 . gain matching vs. frequency, 1 k source imbalance rev. 0 | page 9 of 20
AD8244 data sheet 0.01 0.1 1 10 100 1k ?40 ?20 0 20 40 60 80 input bias current (pa) temper a ture (c) 1 1689-016 r e p r e s e n t a t i v e s a m p l e figure 16 . input bias current vs. temperature ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 ?40 ?20 0 20 40 60 80 system error (v/v) temper a ture (c) re p re se n t at i v e s am p l e s n o rm ali z e d at 2 5c v i n = 3 v 1 1689-017 figure 17 . system error vs. temperature, normalized at 25c 100 120 140 160 180 200 220 240 ?40 ?20 0 20 40 60 80 supp l y current per amplifier (a) temper a ture (c) v s = 15 v v s = + 5 v 1 1689-018 figure 18 . supply current vs. temperature ?15 ?10 ?5 0 5 10 15 ?40 ?20 0 20 40 60 80 shor t -circuit current (ma) temper a ture (c) i sh or t + i sh or t ? v s = 5 v 1 1689-019 figure 19 . short - c ircuit current vs. temperature 0 3 6 9 12 15 18 output vo lt age swing (mv) referred t o supp l y vo lt ages supp l y vo lt age (v s ) ?40 c +2 5 c +8 5 c +v s ?50 ?100 ?150 ?200 +50 +100 +150 +200 ?v s r l = 100 k? 1 1689-020 figure 20 . output voltage swing vs. supply voltage, r l = 1 0 0 k 0 3 6 9 12 15 18 output vo lt age swing (v) referred t o supp l y vo lt ages supp l y vo lt age (v s ) ?40 c +2 5 c +8 5 c +v s ?0.1 ?0.2 ?0.3 ?0.4 +0.1 +0.2 +0.3 +0.4 ?v s r l = 10 k? 1 1689-021 figure 21 . output voltage swing vs. supply voltage, r l = 10 k rev. 0 | page 10 of 20
data sheet AD8244 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 100 1k 10k 100k 1m output vo lt age swing (v) load resis t ance () ? 40 c + 2 5 c + 8 5 c 1 1689-022 figure 22 . output voltage swing vs. load resistance 10 100 1m 10m output vo lt age swing (v) referred t o supp l y vo lt ages output current (a) +v s ?0.2 ?0.4 ?0.6 ?0.8 +0.2 +0.4 +0.6 +0.8 ?v s ?40 c +2 5 c +8 5 c 1 1689-023 figure 23 . output voltage swing vs. output current ?2 0 2 4 6 8 10 ?15 ?10 ?5 0 5 10 15 input bias current (pa) input vo lt age (v) v s = 15 v v s = 5 v 1 1689-026 figure 24 . input bias current vs. input voltage ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 ? 10 ? 8 ? 6 ? 4 ? 2 0 2 4 6 8 10 nonlinearit y (ppm) output vo lt age (v) r l = 100k? r l = 10k? r e p r e s e n t a t i v e s a m p l e v s = 15 v 1 1689-025 figure 25 . nonlinearity , v s = 15 v ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 3 2 1 0 ?1 ?2 ?3 nonlinearit y (ppm) output vo lt age (v) r l = 100k? r l = 10k? r e p r e s e n t a t i v e s a m p l e v s = 5 v 1 1689-126 figure 26 . nonlinearity, v s = 5 v 1 10 100 1k 0.1 1 10 100 1k 10k noise (nv/hz) frequenc y (hz) 1 1689-028 figure 27 . voltage noise spectral density vs. frequency rev. 0 | page 11 of 20
AD8244 data sheet 200nv/div 1s/div 1 1689-029 figure 28 . 0.1 hz to 10 hz voltage noise ?5 ?4 ?2 ?3 ?1 0 1 2 3 4 5 0 10 20 30 40 50 60 70 80 change in offset vo lt age (v) w arm-u p time (seconds) v s = 15 v 1 1689-129 figure 29 . change in offset voltage vs. warm - u p time i n p u t v o lt age o u t p u t vo lt age v s = 5 v v in = 5 .5v 2v/div 1ms/div 1 1689-030 figure 30 . no phase reversal 0 5 10 15 20 25 30 100 1k 10k 100k 1m maximum output vo lt age (v p-p) frequenc y (hz) v s = 15 v v s = 5 v v s = + 5 v 1 1689-031 figure 31 . large signal frequency response 18.4s to 0.01% 5v / d i v 0 . 002 %/ d i v 5 0s / d i v 1 1689-032 figure 32 . large signal pulse response and settling time , r l = 10 k, c l = 100 pf 0 5 10 15 20 25 30 35 40 2 4 6 8 10 12 14 16 18 20 settling time (s) ste p size (v) se tt le d t o 0 . 01 % 1 1689-033 figure 33 . settling time vs. step size, r l = 10 k, c l = 100 pf rev. 0 | page 12 of 20
data sheet AD8244 20mv/div 4s/div 1 1689-036 figure 34 . small signal pulse response, r l = 10 k?, c l = 100 pf 25mv/div 4s/div 1 1689-037 c l = no load c l = 100pf c l = 200pf figure 35 . small signal pulse response with various capacitive loads , r l = no load ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 10 100 1k 10k 100k 1 1689-136 channe l isol a tion (db) frequenc y (hz) t y p i c a l c h a nn e l- t o-c h a nn e l i s o l a t i o n c h a nn e l a f u ll y d r i v e n r l = 10 k? 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 input capacitance (pf) v in (v) referred to +v s input capacitance does not depend on negative supply voltage +v s 1 1689-038 figure 37 . input capacitance vs . i nput voltage (v in ) referred to +v s rev. 0 | page 13 of 20
AD8244 data sheet theory of operation +v s +v s ?v s +v s ?v s ?v s i n o u t 500 ? 1 1689-039 figure 38 . simplified schematic overview the AD8244 is a precision, quad, fet input , unity - gain buffer that is designed to isolate very large source impedances from the rest of the signal chain. n - channel jfets are used as the input transistors to provide a low offset ( 350 v maximum ) , low noise ( 13 nv/ hz typical ) , high impedance ( more than 10 t? ) input stage that operates right down to the negative supply vo ltage. using a new drift trimming method, the b grade AD8244 is able to achieve very low offset voltage over temperature ( 0.5 45 mv ma ximum ), and it introduce s minimal system error over temperature. the AD8244 design is optimized for high precision applications, such as buffers for biopotential electrodes , where it is import ant that buffers have very high impedance inputs and channels that match closely . because the AD8244 fits into a 10- lead package, whereas a quad op amp requires a minimum of 14 lead s, routing spac e is reduced and parasitics from the feedback traces are eliminated. furthermore, the flexi ble design and the high channel density of the AD8244 allow it to be used in the signal chain anywhere a unity - gain buffer is needed. guarding when using low input bias current fet input amplifiers, designers must pay careful attention to voltage gradients from the input node to adjacent conductors on the board. t h ese gradients can crea te leakage currents that overwhelm the input impedance and bias current performance of the fet input. these leakage currents get much worse with contamination, humidity, and temperature. guarding techniques can be used to protect against parasitic leakage currents by greatly reducing the voltage gradient seen by the input node . physically, a guard is a low impedance conductor that surrounds a high impedance node and is raised to the voltage of that node . it serves to buffer leakage by diverting it away from the sensitive node and into the low impedance guard . a complication results from the fact that many traditional op amp pinouts place a supply pi n next to the noninverting input . the only way to guard the input of one of these op amp s is to route the guard trace between the i nput pin and the supply pin. t races can be routed between pins for large packages , such as dip or even soic ; however, the board area consumed by these packages is prohibitive for many modern applications . 3 ?v s 4 +v s out 8 7 6 5 1 ?in 2 +in 3 ?v s 4 8 +v s 7 out 6 5 large footprint packages small footprint packages input input guard guard guard guard single op amp single op amp *leakage path from +in to ?v s causes large input current ?in 2 +in 1 1 1689-041 figure 39 . single op amp guarding patterns the AD8244 solves this problem with a unique pinout that naturally isolates the high impedance inputs from the low impedance nodes, such as the supplies and outpu ts of the other buffers. additionally, the buffers of the AD8244 can be used to guard their own inputs , reducing the voltage gradient seen by the input to only the low offset voltage of the buffer . the AD8244 facilitates this by making guard traces easy to route without the need for traces to go between pins. out a in a 1 2 3 +v s guard trace surrounds input node guard trace from sensor solder mask removed in a out a 1 1689-042 AD8244 figure 40 . guarding with the AD8244 rev. 0 | page 14 of 20
data sheet AD8244 input protection all terminals of the AD8244 are protected against esd. in addition, the input structure allows for dc overload con ditions up to a diode drop above the positive supply and a diode drop below the negative supply. voltages more than a diode drop beyond the supplies cause the esd diodes to conduct and enable current to flow through the diode. therefore, use an external re sistor in series with each of the inputs to limit current for voltages beyond the supplies. in either scenario, the AD8244 input safely handles a continuous 6 ma current at room temperature. for applications where the AD8244 encounters extreme overload voltages, as in cardiac defibrillators, use external series resistors and low leakage diode clamps, such as fjh1100 or bav199l . layout considerations the inputs of the AD8244 buffers are extremely high impedance . shunt impedances from leakage resistance and parasitic capacitance in the printed circuit board (pcb) layout can sever ely degrade the performance of the jfet input. if a buffer output is used to surround the corresponding input node, leakage resistance and parasitic capacitance from the layout can be kept extremely low. remove s older mask from the guard traces to guard ag ainst surface leakage due to contamination. in addition to the guard traces on the primary side , route a guard trace around a ny vias in the input net on the other side of the board as well . k eep the parasitic capacitance seen by the output small to maintain the optimum step response. amplifiers use d in the same signal path, such as buffering the voltage for two inputs of an in - amp or diff erence amp lifier , must have matched impedance in the input traces. this include s matched length and symmetrical traces. place a ny input resistors close to the AD8244 inputs to avoid interaction with trace parasitics. if one of the channels is not in use, connect the input to a voltage that is within its linear range to avoid overdrive conditions that can interfere with other channels. leave t he output unconnected. place d ecoupling capacitors , such as 0.1 f , near the AD8244 . larger capacitors, such as 10 f , can be used farther away from the device . differential signal chains the AD8244 can be used to buffer the inputs of difference amplifiers and instrumentation amplifiers to take advantage of qualities of the jfet input. in applications such as these, which use two channels of the AD8244 to buffer the positive and negative of a differential signal path , it is the mismatch between the channels, rather than the absolute error, that introduces error into the system . the AD8244 is de signed so that the channels closely match and can be used in differential circuits with excellent results . channel - to - channel m atching errors are specified to aid in the design process . when driving the inputs of an instrumentation amplifier , difference am plifier, or other differential input circuit, the g ain matching from channel to channel defines the common - mode rejection ratio ( cmrr ) error introduced to the system by the AD8244 . the unit conver sion is as follows: cmrr (db) = 20 log 10 ( 100/ gain matching (%)) t he jfet pinch - off voltage can vary from channel to channel and cause additional mismatch when the jfet begins to saturate near the positive rail. t he cmrr error is minimized by keeping the input voltage away from the positive input range limit . because the input impedance is very high , the cmrr achieved in differential syst ems stays high , even with large or mismatched source resistance. see the typical performance characteristics section for more information. low output i mpedance vs . frequency the closed - loop output impedance of the AD8244 increases at higher frequencies when the loop gain is reduced , as shown in figure 12. the AD8244 drives 200 pf directly with slight ringing, as shown in figure 35. by placing a small resistor in series with the output, t he capacitive load drive of the AD8244 can be increased. for applications that need the AD8244 input performance and very low out put impedance over frequency, such as driving a cable shield, a switching load, or a large amount of capacitance at high frequencies , an op a mp can be added in a configuration , such as the one in figure 41 . this configuration takes advantage of the op amp output impedance at low frequencies , and the load capacitor reduces the output impedanc e at high frequencies. typically , r o c l is approxima tely equal to r f c f . 1/4 AD8244 a1 v out c f r f v in r o c l r s 1 1689-043 figure 41 . adding an op amp for low output impedance rev. 0 | page 15 of 20
AD8244 data sheet applications information electro c ardiogram (ecg) in an ecg system, mismatches between the source impedance of different leads , working against the input impedance of the front - end amplifier , can create unbalanced resistor divider s that potentially reduce the system cmrr . when presented to a moderately high input impedance amplifier, t he combine d impedance of the skin, electrolyte, electrodes, and the protection resistors can be enough to cause power line noise pickup, current noise issues, and signal division. dry electrode systems , which are becoming increasingly common and have significantly higher source impedance , are especially sensitive to these errors. typical ly , a high input impedance , low bias current , fet input op amp is used to buffer the electrode signal before it is presented to an instrumentation amplifier. this buffer solves the majority of these problems ; however, when an instrument is in the field , it can be subject to dust pickup and humidity. if the op amp input is not guard ed , t hese environmental factors can create unwante d leakage currents that bring back the previous issues from input impedance that is not sufficiently high . the AD8244 is configured to make it simple to guard the input s from parasitic resistance and capacitance while it also drives the instrum entation amplifier inputs , creating a more robust design , while saving power and board space. the cmrr of the AD8244 driving an instrumentation amplifier initially depends on the gain matching for the chosen supplies and voltage range, as well as the instrumentation amplifier used, but it can be improved with design techniques such as right leg drive (rld) or digital filtering. filtering in filtering applications, it is generally r ecommended to use capacitors such as c0g or np0 ceramics for distortion and dielectric absorption performance. these types of capacitors do not have a high volumetric efficiency and are available in values up to the tens of nanofarads , depending on the cas e size and voltage rating. for a given cutoff frequency, using smaller capacitors requires larger resistor values. at low frequencies where the resistor values become very large, the bias current of a typical op amp can introduce significant offsets and a dditional noise. the subpicoampere bias current of the AD8244 allows resistor values in the tens of megaohms with no additional error while providing an excellent low power, small footprint soluti on for filter design. between the four channels of the AD8244 , a filter with more than eight poles can be implemented while using less space than the same filter with a quad op amp. sallen - key low - pass filter 1/4 AD8244 v out c 1 v in c 2 r 1 r 2 1 1689-143 figure 42 . sallen - key low - pass filter the following equations describe the corner frequency, f c , and quality factor, q, for the low - pass filter case of the sallen - key topology , shown in figure 42: f c = 1/(2 c2 c1 r2 r1 ) q = ( c2 c1 r2 r1 )/( c2 ( r1 + r2 )) for an example of a design with this topology, choose a filter where q = 0.707 and r1 = r2 = r. this requires that c1 = 2 c2 . the corner frequency equation can now be simplified to f c = 1/(2 r c2 2) if an available capacitor , such as 1 nf , is chosen for c2, r can be written in terms of the desired cutoff frequency: r = 1/( 2 2 1 nf f c ) = 112.5 m? hz ( that is, r = 750 k? for f c = 150 hz) sallen - key high - pass filter 1/4 AD8244 v out c 1 v in c 2 r 1 r 2 1 1689-144 figure 43 . sallen - key high - pass filter the high - pass filter case of the sallen - key topology has the same corner frequency eq uation as the low - pass filter. however, t he equation for q changes to q = ( c2 c1 r2 r1 )/( r1 ( c1 + c2 )) in this case, a q of 0.707 is achieved with c1 = c2 = c, and r1 = ? r2, which is a symmetrical result to the low - pass filter case. the corner frequency then simplifies to f c = 1/( 2 r2 c ) for a low corner frequency, a larger available capacitor such as 22 nf can be chosen, yielding the following expression for r2: r 2 = 10.2 m? hz ( that is, a 0.5 hz filter requires r1 = 10 m? an d r2 = 20 m?) rev. 0 | page 16 of 20
data sheet AD8244 twin - t notch filter 1/4 AD8244 v out c 2c r/2 v in c (1 ? k) r' k r' 1 1689-145 r r c = 7500pf 60hz: r = 375k? 50hz: r = 422k? 1/4 AD8244 figure 44 . twin - t notch filter the following equations describe the parameters of th e twin - t notch filter with active feedback shown in figure 44: f o = 1/(2 rc ) q = 0.25/(1 ? k ) w here k is an attenuation factor from 0 to 1 , as shown in figure 44 . a k of either 0 or 1 can be achieved with only one buffer . one of the best things about this filter is that f o and q are independent, which allows for easy tuning of filter characteristics . however, d esigners use the twin - t n otch filter sparingly in production designs because of its sensitivity to component tolerances, which affect both the depth and the frequency of the notch. reducing the q is one way to ensure that the desired frequency ha s sufficient attenuation independent of component varia nce and drift ; however, reducing the q also linearly increases the distance between the pass bands. the notch depth can be improved and the stop - band width decreased simultaneously by cascading multipl e filter stages. to illustrate the benefit of cascading stages, figure 45 shows the response of two filters, both designed to provide greater than 26 d b of attenuation at 60 hz 5% , which allows for component tolerance . the single stage filter requires a q of 0.5 and results in a ? 3 db notch bandwidth of 120 hz. the two stage filter has a q of 2.25 for each stage, and the ?3 db notch bandwidth is reduce d to about 40 hz. ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 10 100 1k magnitude (db) frequenc y (hz) ?26db from 57hz to 63hz single stage notch two stage cascaded notch 1 1689-046 figure 45 . cascading notch filters photodiode amplifier photodiodes in precision circuits are typically measured in photovoltaic mode , in which there i s no reverse bias voltage. two benefits to this measurement mode are that there is no dark current , and the output is linearly related to the light intensity. however , in photovoltaic mode , the signal current can be very small, requiring a high gain transi mpedance amplifier ( tia ) . there are a limited number of amplifiers suited for building tias for measuring photodiode s or other low current sensors , which can make it difficult to achieve high performance . using an AD8244 as the interface to the photodiode eliminates the need for a low bias current op amp, allowing optimization of other parameters , such as precision, slew rate, output drive, board space, and c ost. as with any composite amplifier, it is important to pay special attention to stability. the unity - gai n crossover frequency of the op amp must be less than the AD8244 bandwidth for this config uration to be unity - gain s table. the noise gain of the op amp varies with the shunt resistance of the diode , which is temperature dependent. 1/4 AD8244 v out c f r f i phd guard a1 1 1689-044 figure 46 . AD8244 in a photodiode application rev. 0 | page 17 of 20
AD8244 data sheet low noise , jfet input buffer the voltage noise of the AD8244 can be reduced by placing multiple buffers in parallel. for example, two buffers in parallel reduc e the voltage noise by 2 , or all four buffers placed in parallel act as a buffer with ? the noise. the trade - offs to this method are increased bias current, current noise, and input capacitance. place a small resistor, such as 50 ? , between the outputs to avoid extra current flow due to the slight differences between each output . for less power sensitiv e applications, t hese 50 ? resistors can be omitted to boost the available output current . v out v in r s AD8244 r o 1/4 AD8244 r o 1/4 AD8244 r o 1/4 AD8244 r o 1/4 1 1689-045 figure 47 . reducing the voltage noise rev. 0 | page 18 of 20
data sheet AD8244 outline dimensions c o m p l i a n t t o j e d e c s t a n d a r d s m o - 1 8 7 - b a 0 9 1 7 0 9 - a 6 0 0 . 7 0 0 . 5 5 0 . 4 0 5 1 0 1 6 0 . 5 0 b s c 0 . 3 0 0 . 1 5 1 . 1 0 m a x 3 . 1 0 3 . 0 0 2 . 9 0 c o p l a n a r i t y 0 . 1 0 0 . 2 3 0 . 1 3 3 . 1 0 3 . 0 0 2 . 9 0 5 . 1 5 4 . 9 0 4 . 6 5 p i n 1 i d e n t i f i e r 1 5 m a x 0 . 9 5 0 . 8 5 0 . 7 5 0 . 1 5 0 . 0 5 figure 48 . 10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding AD8244armz ?40c to +85c 10- lead mini small outline package [msop] , standard grade rm - 10 y54 AD8244armz -r7 ?40c to +85c 10- lead mini small outline package [msop] , standard g rade, 7 tape and reel rm - 10 y54 AD8244brmz ?40c to +85c 10- lead mini small outline package [msop] , high performance grade rm - 10 y55 AD8244brmz -r7 ?40c to +85c 10- lead mini small outline package [msop] , high performance grade , 7 tape and reel rm - 10 y55 1 z = rohs compliant part. rev. 0 | page 19 of 20
AD8244 data sheet notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11689 - 0- 10/13(0) rev. 0 | page 20 of 20

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